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The pulse width prediction control technique has been widely used in AC-DC converters with power factor correction in boost topology, where satisfactory results have been reported without the need to use classic control laws. However, this technique has not been explored for other types of ACDC converters with power factor correction. In this work, the use of this technique is proposed in an AC-DC converter with power factor correction in a half-bridge boost topology. This topology presents high efficiency because it uses the least number of semiconductors compared to other topologies. In this technique the duty cycle is predicted by processing the average values of state and input variables of the converter in half bridge boost topology, using only four multiplications and five additions, which implies less complexity in its implementation. For its validation simulations were performed using MATLAB R Simulink, where it was possible to observe values of power factor and THD comparable with other control methods such as non-linear carrier control, and conventional analog control, both reported in the literature.

La técnica de control de predicción de ancho de pulsos ha sido ampliamente utilizada en convertidores AC-DC con corrección de factor de potencia en topología boost, donde se han reportado resultados satisfactorios sin necesidad de usar leyes clásicas de control. Sin embargo, ésta técnica no ha sido explorada para otros tipos de convertidores AC-DC con corrección de factor de potencia. En este trabajo, proponemos el uso de ésta técnica en un convertidor AC-DC con corrección de factor de potencia en una topología de boost medio puente. Esta topología presenta una alta eficiencia dado que usa el menor número de semiconductores comparada con otras topologías. En ésta técnica el ciclo de trabajo es predicho al procesar los valores promedio de las variables de entrada y estado del convertidor en topología boost medio puente, usando únicamente cuatro multiplicaciones y cinco adiciones, lo que implica menos complejidad en su implementación. Para su validación, se realizaron simulaciones usando MATLAB R Simulink, donde fue posible observar valores de factor de potencia y THD comprables con otros métodos de control como control de portador no lineal y control convencional análogo, ambos reportados en la literatura.

Currently, most electronic equipment such as power sources, battery chargers, appliances, communication systems, medical equipment, among others, need a constant DC voltage bus from the AC line. For this they include in the input stage the simplest and most conventional AC-DC converter (SC), which comprises a diode bridge and an electrolytic capacitor with a high capacitance value ^{[}^{1}^{]}. The SC is widely used because of its very low cost; however, the waveform that the converter absorbs from the AC line is not sinusoidal and has a high crest factor, due to the small conduction angle used by the electrolytic capacitor to charge ^{[}^{2}^{]}. For this reason, the waveform of the line current has a high total harmonic distortion that produces the following disadvantages: first, reduction of the power factor, which implies a decrease in the AC line available power ^{[}^{3}^{]}; second, harmonics injection to the line voltage that interfere with other electronic equipment connected to the same line ^{[}^{4}^{]}; finally, line voltage instability ^{[}^{5}^{]}.

Consequently, the SC cannot meet the IEC-61000-3-2 and IEEE Std 519 European and/or American standard respectively. These standards impose the limits on AC current harmonics, as well as in total harmonic distortion of the electronic equipment that is fed by the AC line ^{[}^{6}^{]}. In order to meet these standards, different studies in the area of power electronics have focused on improving the power factor of electronic equipment that are connected to the line.

For this purpose, AC-DC converters with power factor correction (CPFC) are the best alternative ^{[}^{7}^{] [}^{8}^{]}. Several authors have analyzed the operation of the CPFC topologies, from the most classic such as: boost ^{[}^{9}^{] [}^{10}^{]}, buck-boost ^{[}^{11}^{]}, flyback ^{[}^{12}^{] [}^{13}^{]} and half bridge boost ^{[}^{14}^{] [}^{15}^{]}, up to the most recent: no diode bridge ^{[}^{2}^{] [}^{16}^{] [}^{17}^{]}, interleaved ^{[}^{18}^{]} and flyback with dual-purpose inverter ^{[}^{19}^{]}. Within these, the AC-DC converters with power factor correction in half bridge boost topology (CPFC-HBB) has the simplest conversion circuit and with fewer switches^{[}^{20}^{]}, so the main advantage of the CPFC-HBB is that it presents high efficiency, since at any time there is only a voltage drop, which is produced by the working semiconductor ^{[}^{21}^{]}. Another advantage of the CPFC-HBB is to allow its power flow to be bidirectional; this explains why the CPFCHBB is widely used in power factor correction applications [22].

On the other hand, other authors have studied and implemented control methods for the CPFC-HBB such as: conventional analog ^{[}^{7}^{]}, by replacing a boost diode and inductor with a switch and transformer, respectively [23], current-by hysteresis ^{[}^{14}^{]} [24], non-linear Lyapunov technique [25] [26] and non-linear carrier control [27] [28], or current sensor-less control [29].

The emergence of low-cost microprocessors, digital signal processors (DSP) and programmable gate array (FPGA) has made it possible for new control strategies to emerge, which have advantages such as programmability and lower sensitivity to parameters variation. Some of these control strategies that predict the CPFC duty cycle from the inductance, reference current, input voltage and output voltage reference, have been introduced in previous works [30] [31], nevertheless, these control strategies were implemented in CPFC in boost topology .

In this work, we propose a strategy for predicting the duty cycle for a CPFC-HBB, in order to obtain a high power factor. The aim of this work is to design a control strategy for CPFC-HBB, by means of predicting the duty cycle starting from the average model. This work is divided as follows: in Section 2, a rigorous and detailed analysis of the proposed control strategy is presented using the average circuit model; in section 3, the simulation results of the proposed control that was implemented in MATLAB R Simulink; in section 4, the conclusions and future work.

The CPFC-HBB circuit used with the predictive control strategy is shown in _{1}, S_{2}) each with their respective intrinsic diode, an inductance on the AC side _{1}, _{2}) and a load resistance

The analysis of the proposed control strategy is derived from assuming that all CPFC-HBB circuit components are ideal. To begin with, the inductance voltage equation that is given by:

Here ^{
^
}
_{L} and ^{
^
}
_{L} are the instantaneous current and voltage of the inductance respectively. By solving for ^{
^
}
_{L} and integrating from _{s}:

Here ^{
^
}
_{L}
^{
^
}
_{L}(t + _{s}
^{[}^{20}^{]} it was determined that the left side of equation 2 is the net change in the inductance current over a switching period, also noting that said change is exactly equal to the switching period for the average slope.

On the other hand, ^{[}^{20}^{]}. _{1} is replaced by a voltage source whose value is equal (1 - d) v_{s}, where d is the duty cycle of S_{1} and _{s} is the sum of the average voltages of capacitors _{2}, likewise, _{2} is replaced by a current source with value equal to (1 - _{L}, where i_{L} is the average current of the inductance.

The ACM is used to obtain expressions that define the state equations averaged over one switching period, to determine the steady-state values CPFC-HBB easily and finally, to simulate efficiently the CPFC-HBB, this means that time and memory storage decreases compared to the simulation using the switches. However, the switch model is useful and necessary to determine currents and peak voltages experienced by the CPFC-HBB.

When applying Kirchhoff's law of voltages around the ACM mesh, composed of v_{g}, L, (1 - _{s} and C_{1}, we obtain the average voltage of inductance VL, which is defined by:

The averaged state variables of the CPFC-HBB are i_{L}, _{1} and _{2}
_{1} and _{2} are changed to the new state variables _{s} and _{d}
_{L} stays the same, then _{s} and _{d} are defined by:

Solving

By substituting equation 6 in 3:

Replacing equation 7 in 2, the duty cycle

When observing

The value of the duty cycle can be known, as long as all the variables to the right of equation 9 are known. However, the inductor current at the end of the switching period i_{L}
_{s}) is unknown. In order to obtain a unit power factor in the CPFC-HBB, the value of this current must be proportional to the input voltage _{g} value evaluated in _{s}
_{g} (t) is a good approximation of _{s}), so that equation 9 is changed to:

Here _{g} is the reference current and _{s}, _{s} and the gain of block _{g} to the multiplier.

We should also mention that the output voltage is controlled to follow the reference voltage _{ref}
_{ref} and the division by _{d}

The duty cycle _{g}
_{L}, the input voltage _{g} current and the voltage difference _{d}, together with the constant terms mentioned above; likewise, it is shown in equation 11 that only four multiplications and five additions are needed to implement the computation of

The inductance current is controlled by _{s} the inductance current i_{L} is not exactly the same, but very close to the reference current _{g}

The block diagram of the pulse width prediction control (PWPC) proposed for the CPFC-HBB is shown in _{s}

With the proposed PWPC, the current inductance i_{L} of the CPFC-HBB follows the reference current and the output voltage vs of the CPFC-HBB follows the reference voltage. On the other hand, ^{[}^{9}^{]} confirmed the existence of the voltage imbalance in the capacitors; they also researched the causes that produced it and provided a control scheme to eliminate it, this scheme consists in adding the difference between _{1} and _{2} to the reference current multiplied by a gain. The PWPC proposed in this work, eliminates the capacitor voltage imbalance, since as can be seen in ^{[}^{9}^{]} suggests that the value of the block gain processing the difference between _{g}, and

A CPFC-HBB with the proposed PWPC strategy was simulated using MATLAB R Simulink, with the circuit parameters that are shown in

The experimental results show that a high power factor is obtained under stationary and transient conditions, these results are shown in subsections 3.1 and 3.2.

Voltage and the input current _{g} and _{g}
_{o} = 200 mA, are shown in

The power factor (PF) with this load condition is 0.9954 and the total harmonic distortion _{g} and _{g} for I_{o} = 100 mA, are shown in _{g} and _{g} for I_{o} = 50 mA, are shown in

Test results show that the proposed control method for CPFC-HBB, can achieve a near unit power factor and low total harmonic distortion, in steady state condition and with different load current values. In this way, the proper functioning of the PWPC proposed in steady state is shown. Increased in step from 150 mA to 200 mA is shown in _{1} and v_{2} is around 10 V.

Likewise, when _{o} is decreased in step from 200 mA to 150 mA is shown in _{1} and v_{2} is around 10 V. On the other hand, the transient response when vg is increased in step from 120V to 140 V, is shown in

Similarly, the transient response when vg is reduced in step from 140 V to 120 V is shown in _{1} and v_{2} is around 10 V. In addition, in Figs. 10-13, we can see that within the transient periods, the input current remains sinusoidal. We can also see that _{1} and _{2}, are absolutely equal in the steady state and transient conditions, this confirms what was said in section 2, that the proposed control includes the scheme that was presented in ^{[}^{9}^{]}, to eliminate the problem of voltage imbalance in capacitors.

^{[}^{5}^{]}, where the analysis is shown in detail CPFC-HBB, and the implementation of internal current loop with current averaging technique using a PID controller; the work presented in ^{[}^{17}^{]} is also included, where a simple analog control was proposed and implemented for the CPFC-HBB with the non-linear carrier control method.

Observing ^{[}^{5}^{] [}^{17}^{]}; second, the total harmonic distortion of the CPFC-HBB with the proposed PWPC is lower compared to ^{[}^{5}^{] [}^{17}^{]}; third; the transient response of CPFC-HBB with PWPC proposed is much faster than that presented in ^{[}^{5}^{] [}^{17}^{]}; finally, the voltage drop of the CPFC-HBB capacitors with the proposed PWPC is the same as in ^{[}^{17}^{]} and lower than in ^{[}^{5}^{]}.

Values obtained from hardware experimentation.

In this paper we presented a control technique for the prediction of the pulse width applied to an AC-DC converter with power factor correction, in half bridge boost topology.

The results show a power factor of 0.9954, transient response times to load change from 75% to 100% and

It is also noteworthy that the algorithm proposed for the duty cycle prediction was obtained from the variables of state and average input, since it was based on the ACM. This implies an advantage over the techniques reported in literature that use instantaneous values of these variables, making measurement more difficult.

In future work, the converter will be implemented in hardware with the proposed control technique, verifying the results experimentally and comparing the resulting power factor with other existing techniques. In addition, the algorithm will be implemented to other topologies of AC-DC converters with power factor correction

^{th}Internatonal Conference on Power Electronics, 2008, pp. 426-430.

Bayona, J.F., Guarnizo J.G., Gelvez, N., Pulse width Prediction Control Technique Applied to a Half-Bridge Boost, TECCIENCIA, Vol. 13 No. 25, 47-54, 2018. DOI: